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1 description the cat5401 is four digitally programmable potentiometers (dpps?) integrated with control logic and 16 bytes of nvram memory. each dpp consists of a series of 63 resistive elements connected between two externally accessible end points. the tap points between each resistive element are connected to the wiper outputs with cmos switches. a separate 6-bit control register (wcr) independently controls the wiper tap switches for each dpp. associated with each wiper control register are four 6-bit non-volatile memory data registers (dr) used for storing up to four wiper settings. writing to the wiper control register or any of the non-volatile data cat5401 quad digitally programmable potentiometers (dpp) with 64 taps and spi interface features four linear-taper digitally programmable potentiometers 64 resistor taps per potentiometer end to end resistance 2.5k ? , 10k ? , 50k ? or 100k ? potentiometer control and memory access via spi interface: mode (0, 0) and (1, 1) low wiper resistance, typically 80 ? ? ? ? ? nonvolatile memory storage for up to four wiper settings for each potentiometer automatic recall of saved wiper settings at power up 2.5 to 6.0 volt operation standby current less than 1 a 1,000,000 nonvolatile write cycles 100 year nonvolatile memory data retention 24-lead soic, 24-lead tssop and bga commercial and industrial temperature ranges pin configuration functional diagram ? 2003 by catalyst semiconductor, inc. characteristics subject to change without notice preliminary information document no. 2010, rev. e registers is via a spi serial bus. on power-up, the contents of the first data register (dr0) for each of the four potentiometers is automatically loaded into its respective wiper control register. the cat5401 can be used as a potentiometer or as a two terminal, variable resistor. it is intended for circuit level or system level adjustments in a wide variety of applications. it is available in the 0 c to 70 c commercial and -40 c to 85 c industrial operating temperature ranges and offered in a 24-lead soic and tssop package or in the chip scale bga. bga top view - bump side down r h0 w0 w2 w3 w1 h1 h2 h3 r r r r l0 l1 l2 l3 r r r wiper control registers nonvolatile data registers spi bus interface control logic sck si wp a0 a1 r r r r cs so h a l o g e n f r e e tm l e a d f r e e 1 2 3 4 a b c d e f r w0 cs a 1 r l1 r l0 wp si r w1 v cc r h0 r h1 v ss nc r h3 r h2 nc r l3 so hold r w2 r w3 a 0 sck r l2 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 cat 5401 v cc r l0 r h0 r w0 cs wp si a 1 r l1 r h1 r w1 gnd nc r l3 r h3 r w3 a 0 so hold sck r l2 r h2 r w2 nc 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 cat 5401 si a 1 r l1 r h1 r w1 gnd nc r w2 r h2 r l2 sck hold wp cs r w0 r h0 r l0 v cc nc r l3 r h3 r w3 a 0 so soic package (j, w) tssop package (u, y)
2 cat5401 document no. 2010, rev. e preliminary information being initiated. a low to high transition on cs after a valid write sequence is what initiates an internal write cycle. wp wp wp wp wp : write protect wp is the write protect pin. the write protect pin will allow normal read/write operations when held high. when wp is tied low, all write operations to the wiper control and data registers are inhibited. wp going low while cs is still low will interrupt a write to the registers. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation. hold hold hold hold hold : hold the hold pin is used to pause transmission to the cat5401 while in the middle of a serial sequence without having to re- transmit entire sequence at a later time. to pause, hold must be brought low while sck is low. the so pin is in a high imped- ance state during the time the part is paused, and transitions on the si pins will be ignored. to resume communication, hold is brought high, while sck is low. ( hold should be held high any time this function is not being used.) hold may be tied high directly to vcc or tied to vcc through a resistor. pin description pin pin pin (soic) (tssop) (bga) name function 1 19 c1 vcc supply voltage 220b1r l0 low reference terminal for potentiometer 0 321c2r h0 high reference terminal for potentiometer 0 422a1r w0 wiper terminal for potentiometer 0 523a2 cs chip select 624b2 wp write protection 7 1 b3 si serial input 8 2 a3 a1 device address 93a4r l1 low reference terminal for potentiometer 1 10 4 c3 r h1 high reference terminal for potentiometer 1 11 5 b4 r w1 wiper terminal for potentiometer 1 12 6 c4 gnd ground 13 7 d4 nc no connect 14 8 e4 r w2 wiper terminal for potentiometer 2 15 9 d3 r h2 high reference terminal for potentiometer 2 16 10 f4 r l2 low reference terminal for potentiometer 2 17 11 f3 sck bus serial clock 18 12 e3 hold hold 19 13 e2 so serial data output 20 14 f2 a0 device address, lsb 21 15 f1 r w3 wiper terminal for potentiometer 3 22 16 d2 r h3 high reference terminal for potentiometer 3 23 17 e1 r l3 low reference terminal for potentiometer 3 24 18 d1 nc no connect pin descriptions si: serial input si is the serial data input pin. this pin is used to input all opcodes, byte addresses and data to be written to the cat5401. input data is latched on the rising edge of the serial clock. so: serial output so is the serial data output pin. this pin is used to transfer data out of the cat5401. during a read cycle, data is shifted out on the falling edge of the serial clock. sck: serial clock sck is the serial clock pin. this pin is used to synchronize the communication between the microcontroller and the cat5401. opcodes, byte addresses or data present on the si pin are latched on the rising edge of the sck. data on the so pin is updated on the falling edge of the sck. a0, a1: device address inputs these inputs set the device address when address- ing multiple devices. when these pins are left floating the default values are zero. a total of four devices can be addressed on a single bus. a match in the slave address must be made with the address input in order to initiate communication with the cat5401. r h , r l : resistor end points the four sets of r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. r w : wiper the four r w pins are equivalent to the wiper terminal of a mechanical potentiometer. cs cs cs cs cs : chip select cs is the chip select pin. cs low enables the cat5401 and cs high disables the cat5401. cs high takes the so output pin to high impedance and forces the devices into a standby mode (unless an internal write operation is underway). the cat5401 draws zero current in the standby mode. a high to low transition on cs is required prior to any sequence
3 cat5401 document no. 2010, rev. e preliminary information device operation the cat5401 is four resistor arrays integrated with spi serial interface logic, four 6-bit wiper control registers and sixteen 6-bit, non-volatile memory data registers. each resistor array contains 63 separate resistive elements connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l ). r h and r l are symmetrical and may be interchanged. the tap positions between and at the ends of the series resistors are connected to the output wiper terminals (r w ) by a cmos transistor switch. only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. data can be read or written to the wiper control registers or the non-volatile memory data registers via the spi bus. additional instructions allows data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. also, the device can be instructed to operate in an "increment/decrement" mode. serial bus protocol the cat5041 supports the spi bus data transmission protocol. the synchronous serial peripheral interface (spi) helps the cat5401 to interface directly with many of today's popular microcontrollers. the cat5041 contains an 8-bit instruction register .the instruction set and the operation codes are detailed in the instruction set table 3. after the device is selected with cs going low the first byte will be received. the part is accessed via the si pin, with data being clocked in on the rising edge of sck. the first byte contains one of the six op-codes that define the operation to be performed.
4 cat5401 document no. 2010, rev. e preliminary information note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) latch-up protection is provided for stresses up to 100 ma on address and data pins from C 1v to v cc +1v. (3) absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position wh en used as a potentiometer. (4) relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. (5) mi = r tot / 63 or (r h - r l ) / 63, single pot (6) n = 0, 1, 2, ..., 63 potentiometer characteristics over recommended operating conditions unless otherwise stated. symbol parameter test conditions min typ max units r pot potentiometer resistance (-00 ) 100 k ? r pot potentiometer resistance (-50 ) 50 k ? r pot potentiometer resistance (-10 ) 10 k ? r pot potentiometer resistance (-2.5 ) 2.5 k ? potentiometer resistance +20 % tolerance r pot matching 1 % power rating 25 c, each pot 50 mw i w wiper current +6 ma r w wiper resistance i w = +3ma @ v cc =3v 300 ? r w wiper resistance i w = +3ma @ v cc = 5v 80 150 ? v term voltage on any r h or r l pin v ss = 0v gnd v cc v v n noise nv/ hz resolution 1.6 % absolute linearity (3) r w(n)(actual) -r (n)(expected) (6) +1 lsb (5) relative linearity (4) r w(n+1) -[r w(n)+lsb ] (6) +0.2 lsb (5) temperature coefficient of +300 ppm/ c tc rpot r pot tc ratio ratiometric temp. coefficient 20 ppm/ c c h /c l /c w potentiometer capacitances 10/10/25 pf r iso isolation resistance tbd ? fc frequency response r pot = 50k ? 0.4 mhz recommended operating conditions: v cc = +2.5v to +6.0v temperature min max commercial 0 c70 c industrial -40 c85 c absolute maximum ratings* temperature under bias .................. -55 c to +125 c storage temperature ........................ -65 c to +150 c voltage on any pin with respect to v ss (1) ................... -2.0v to +v cc +2.0v v cc with respect to ground ................ -2.0v to +7.0v package power dissipation capability (t a = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c wiper current .................................................. +12ma note: (1) the minimum dc input voltage is C 0.5v. during transitions, inputs may undershoot to C 2.0v for periods of less than 20 ns. maximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
5 cat5401 document no. 2010, rev. e preliminary information d.c. operating characteristics over recommended operating conditions unless otherwise stated. symbol parameter test conditions min typ max units i cc power supply current f sck = 2mhz, so open 1 ma inputs = gnd i sb standby current (v cc = 5.0v) v in = gnd or v cc; so open 1 a i li input leakage current v in = gnd to v cc 10 a i lo output leakage current v out = gnd to v cc 10 a v il input low voltage -1 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 1.0 v v ol1 output low voltage (v cc = 3.0v) i ol = 3 ma 0.4 v pin capacitance (1) applicable over recommended operating range from t a =25 ? c, f=1.0 mhz, vcc=+5.0v (unless otherwise noted). symbol test conditions min typ max units conditions c out output capacitance (so) 8 pf v out =0v c in input capacitance ( cs , sck, si, wp , hold )6pfv in =0v
6 cat5401 document no. 2010, rev. e preliminary information test symbol parameter min typ max units conditions t su data setup time 50 ns t h data hold time 50 ns t wh sck high time 125 ns t wl sck low time 125 ns f sck clock frequency dc 3 mhz t lz hold to output low z 50 ns t ri (1) input rise time 2 s t fi (1) input fall time 2 s t hd hold setup time 100 ns t cd hold hold time 100 ns t wc write cycle time 10 ms t v output valid from clock low 250 ns t ho output hold time 0 ns t dis output disable time 250 ns t hz hold to output high z 100 ns t cs cs high time 250 ns t css cs setup time 250 ns t csh cs hold time 250 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter. note: (1) this parameter is tested initially and after a design or process change that affects the parameter. power up timing (1) over recommended operating conditions unless otherwise stated. symbol parameter min typ max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms a.c. characteristics over recommended operating conditions unless otherwise stated. c l = 50pf
7 cat5401 document no. 2010, rev. e preliminary information write cycle limits over recommended operating conditions unless otherwise stated. symbol parameter min typ max units t wr write cycle time 5 ms figure 1. sychronous data timing figure 2. hold hold hold hold hold timing note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. (3) dashed line= mode (1, 1) reliability characteristics over recommended operating conditions unless otherwise stated. symbol parameter reference test method min typ max units n end (1) endurance mil-std-883, test method 1033 1,000,000 cycles/byte t dr (1) data retention mil-std-883, test method 1008 100 years v zap (1) esd susceptibility mil-std-883, test method 3015 2000 volts i lth (1) latch-up jedec standard 17 100 ma valid in v ih v il t css v ih v il v ih v il v oh v ol hi-z t su t h t wh t wl t v t cs t csh t ho t dis hi-z cs sck si so t ri t fi cs sck hold so t cd t hd t hd t cd t lz t hz high impedance
8 cat5401 document no. 2010, rev. e preliminary information instruction and register description instructions device type / address byte the first byte sent to the cat5401 from the master/ processor is called the device address byte. the most significant four bits of the device type address are a device type identifier. these bits for the cat5401 are fixed at 0101[b] (refer to table 1). the two least significant bits in the slave address byte, a1 - a0, are the internal slave address and must match the physical device address which is defined by the state of the a1 - a0 input pins for the cat5401 to successfully continue the command sequence. only the device which slave address matches the incoming device address sent by the master executes the instruction. the a1 - a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . the remaining two bits in the device address byte must be set to 0. instruction byte the next byte sent to the cat5401 contains the instruction and register pointer information. the four most significant bits used provide the instruction opcode i [3:0]. the r1 and r0 bits point to one of the four data registers of each associated potentiometer. the least two significant bits point to one of four wiper control registers. the format is shown in table 2. table 1. identification byte format id3 id2 id1 id0 0 0 a1 a0 0101 (msb) (lsb) device type identifier slave address table 2. instruction byte format i3 i2 i1 i0 r1 r0 p1 p0 (msb) (lsb) instruction data register wcr/pot selection opcode selection data register selected r1 r0 dr0 0 0 dr1 0 1 dr2 1 0 dr3 1 1 data register selection
9 cat5401 document no. 2010, rev. e preliminary information table 3. instruction set wiper control and data registers wiper control register (wcr) the cat5401 contains four 6-bit wiper control registers, one for each potentiometer. the wiper control register output is decoded to select one of 64 switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written by the host via write wiper control register instruction; it may be written by transferring the contents of one of four associated data registers via the xfr data register instruction, it can be modified one step at a time by the increment/decrement instruction (see instruction section for more details). finally, it is loaded with the content of its data register zero (dr0) upon power-up. the wiper control register is a volatile register that loses its contents when the cat5401 is powered-down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. data registers (dr) each potentiometer has four 6-bit non-volatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the associated wiper control register. any data changes in one of the data registers is a non-volatile operation and will take a maximum of 5ms. write in process the contents of the data registers are saved to nonvolatile memory when the cs input goes high after a write sequence is received. the status of the internal write cycle can be monitored by issuing a read status command to read the write in process (wip) bit. instructions five of the ten instructions are three bytes in length. these instructions are: read wiper control register - read the current wiper position of the selected potentiometer in the wcr write wiper control register - change current wiper position in the wcr of the selected potentiometer read data register - read the contents of the selected data register write data register - write a new value to the selected data register read status - read the status of the wip bit which note: 1/0 = data is one or zero instruction instruction set operation i3 i2 i1 i0 r1 r0 wcr1/ p1 read wiper control register 1001 00 1/0 1/0r ead the contents of the wiper control register pointed to by p1-p0 write wiper control register 1010 00 1/0 1/0w rite new value to the wiper control register pointed to by p1-p0 read data register 10111/01/01/0 1/0r ead the contents of the data register pointed to by p1-p0 and r1-r0 write data register 11001/01/01/0 1/0w rite new value to the data register pointed to by p1-p0 and r1-r0 xfr data register to wiper control register 11011/01/01/0 1/0tr ansfer the contents of the data register pointed to by p1-p0 and r1-r0 to its associated wiper control register xfr wiper control register to data register 11101/01/01/0 1/0tr ansfer the contents of the wiper control register pointed to by p1-p0 to the data register pointed to by r1-r0 global xfr data registers to wiper control registers 00011/01/0 0 0 tr ansfer the contents of the data registers pointed to by r1-r0 of all four pots to their respective wiper control register s global xfr wiper control registers to data register 10001/01/0 0 0 tr ansfer the contents of both wiper control registers to their respective data registers pointed to by r1-r0 of all four pots increment/decrement wiper control register 0010 00 1/0 1/0 enable increment/decrement of the control latch pointed to by p1-p0 wcr0/ p0 read status (wip bit) 0101 00 0 1 read wip bit to check internal write cycle status
10 cat5401 document no. 2010, rev. e preliminary information when set to "1" signifies a write cycle is in progress. the basic sequence of the three byte instructions is illustrated in figure 8. these three-byte instructions exchange data between the wcr and one of the data registers. the wcr controls the position of the wiper. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to non-volatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. four instructions require a two-byte sequence to complete, as illustrated in figure 7. these instructions transfer data between the host/processor and the cat5401; either between the host and one of the data registers or directly between the host and the wiper control register. these instructions are: xfr data register to wiper control register this transfers the contents of one specified data register to the associated wiper control register. xfr wiper control register to data register this transfers the contents of the specified wiper control register to the specified associated data register. global xfr data register to wiper control register this transfers the contents of all specified data registers to the associated wiper control registers. global xfr wiper counter register to data register this transfers the contents of all wiper control registers to the specified associated data registers. increment/decrement command the final command is increment/decrement (figure 5 and 9). the increment/decrement command is different from the other commands. once the command is issued the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. for each sck clock pulse (t high ) while si is high, the selected wiper will move one resistor segment towards the r h terminal. similarly, for each sck clock pulse while si is low, the selected wiper will move one resistor segment towards the r l terminal. see instructions format for more detail. figure 7. two-byte instruction sequence figure 8. three-byte instruction sequence figure 9. increment/decrement instruction sequence 0101 a2 a0 i2 i1 i0 r1 r0 p1 si id3 id2 id1 id0 p0 device id internal instruction opcode address register address pot/wcr address a1 a3 i3 00 i3 i2 i1 i0 r1 r0 id3 id2 id1 id0 device id internal instruction opcode address data register address pot/wcr address wcr[7:0] or data register d[7:0] 0 101 a2 a1 a0 p1 p0 si d7 d6 d5 d4 d3 d2 d1 d0 a3 i3 i2 i1 i0 id3 id2 id1 id0 device id internal instruction opcode address data register address pot/wcr address 0101 a2 a1 a0 r0 p1 p0 si i n c 1 i n c 2 i n c n d e c 1 d e c n r1 a3
11 cat5401 document no. 2010, rev. e preliminary information figure 10. increment/decrement timing limits instruction format read wiper control register (wcr) write wiper control register (wcr) read data register (dr) write data register (dr) sck si r w inc/dec command issued voltage out t wrid read (wip) status device addresses instruction data 0 1 0 1 0 0 a1 a0 0 1 0 1 0 0 0 1 7 6 5 4 3 2 1 0 0 0 0 0 0 0 cs cs w i p device addresses instruction data 010100a1a0 1 0 0 100p1 p0 7 6543210 0 0 cs cs device addresses instruction data 0 1 0 1 0 0 a1 a0 1 1 0 0 r1 r0 p1p0 7 6 5 4 3 2 1 0 cs cs high voltage write cycle device addresses instruction data 0 1 0 1 0 0 a1 a0 1 0 1 1 r1 r0 p1p0 7 6 5 4 3 2 1 0 cs cs cs cs device addresses instruction data 010100a1a0 1 0 1 000p1p07 6 543210 00
12 cat5401 document no. 2010, rev. e preliminary information global transfer wiper control register (wcr) to data register (dr) instruction format (continued) transfer wiper control register (wcr) to data register (dr) transfer data register (dr) to wiper control register (wcr) notes: (1) any write or transfer to the non-volatile data registers is followed by a high voltage cycle after cs goes high. global transfer data register (dr) to wiper control register (wcr) increment (i)/decrement (d) wiper control register (wcr) device addresses instruction 0 101 00a1a000 01r1r0 00 cs cs device addresses instruction 0101 00a1a01000r1r0 00 cs cs high voltage write cycle device addresses instruction data 0 1 0 1 0 0 a1 a0 0 0 1 0 0 0 p1 p0 i/d i/d i/d i/d cs cs ? ? ? device addresses instruction 0 1 0 1 0 0 a1 a0 1 1 0 1 r1 r0 p1 p0 cs cs device addresses instruction 0 1 0 1 0 0 a1 a0 1 1 1 0 r1 r0 p1 p0 cs cs high voltage write cycle
13 cat5401 document no. 2010, rev. e preliminary information notes: (1) the device used in the above example is a cat5401ji-10-te13 (soic, industrial temperature, 10kohm, tape & reel) ordering information 24-lead 300 mil wide soic (j) 0.2914 (7.40) 0.2992 (7.60) 0.394 (10.00) 0.419 (10.65) 0.0926 (2.35) 0.1043 (2.65) 0.0040 (0.10) 0.0118 (0.30) 0.050 (1.27) bsc 0.013 (0.33) 0.020 (0.51) 0 8 0.0091 (0.23) 0.0125 (0.32) 0.010 (0.25) 0.029 (0.75) x 45 0.016 (0.40) 0.050 (1.27) 0.5985 (15.20) 0.6141 (15.60) packaging information prefix device # suffix 5401 j product number cat optional company id i temperature range blank = commercial (0 c to 70 c) i = industrial (-40 c to 85 c) -te13 tape & reel te13: 2000/reel -10 resistance -25: 2.5kohm -10: 10kohm -50: 50kohm -00: 100kohm package j: soic b: bga u: tssop w: soic (lead free, halogen free) y: tssop (lead free, halogen free)
14 cat5401 document no. 2010, rev. e preliminary information packaging information con't 24 lead tssop (u) 6.4 (0.9) 7.8 + 0.1 4.4 + 0.1 pin #1 indent. -a- -b- 0.2 c b a 3.2 all lead tips 7.72 typ 4.16 typ (1.78 typ) 0.42 typ 0.65 typ land p a ttern recommend a tion 0.10 + 0.05 typ 0.19 - 0.30 typ 1.1 max typ 0.1 c all lead tips -c- 0.65 typ 0.3 m a b s c s see detail a 0.09 - 0.20 typ 0.6+0.1 seating plane gage plane 0.25 0 o - 8 o detail a
15 cat5401 document no. 2010, rev. e preliminary information millimeters inches symbol min nom max nom min max package body dimension x a tbd tbd tbd tbd tbd tbd package body dimension y b tbd tbd tbd tbd tbd tbd package height c 0.635 0.505 0.765 0.02500 0.01988 0.03012 package body thickness d 0.433 0.395 0.471 0.01705 0.01555 0.01854 ball height e 0.202 0.110 0.294 0.00795 0.00433 0.01157 ball diameter f 0.284 0.180 0.388 0.01118 0.00709 0.01528 total ball count g 24 ball count x axis h 4 ball count y axis i 6 pins pitch x axis j 0.5 pins pitch y axis k 0.5 edge to ball center (corner) distance along x l tbd tbd tbd tbd tbd tbd edge to ball center (corner) distance along y m tbd tbd tbd tbd tbd tbd packaging information con't 24 ball bga a b 1 2 3 4 a b c d e f top view (bump side down) a b 4 3 2 1 a b c d e f bottom view (bump side up) m k f j note: drawing not to scale = die orientation mark c d e side view (bump side down)
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com publication #: 2010 revison: e issue date: 1/10/03 type: preliminary copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp dpps ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete.

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